Memory devices are typically provided as internal, semiconductor, integrated circuits in computers or other electronic devices. There are many different types of memory including random-access memory (RAM), read only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), and flash memory.
Flash memory devices have developed into a popular source of non-volatile memory for a wide range of electronic applications. Flash memory devices typically use a one-transistor memory cell that allows for high memory densities, high reliability, and low power consumption. Changes in threshold voltage of the cells, through programming of charge storage or trapping layers or other physical phenomena, determine the data value of each cell. Common uses for flash memory and other non-volatile memory include personal computers, personal digital assistants (PDAs), digital cameras, digital media players, digital recorders, games, appliances, vehicles, wireless devices, cellular telephones, and removable memory modules, and the uses for non-volatile memory continue to expand.
Flash memory typically utilizes one of two basic architectures known as NOR flash and NAND flash. The designation is derived from the logic used to read the devices. In NOR flash architecture, a column of memory cells are coupled in parallel with each memory cell coupled to a bit line. In NAND flash architecture, a column of memory cells are coupled in series with only the first memory cell of the column coupled to a bit line.
As semiconductor memory devices continue to scale down to smaller and smaller architectures, problems arise. As just a few examples related to typical NAND floating-gate structures, charge retention become increasingly difficult as dielectric layers become thinner, coupling from neighboring floating gates increases as separation between floating gates is reduced and the likelihood of disturbing the charge of a floating gate during the programming or reading of a neighboring cell increases for similar reasons. Similar problems arise with structures that rely on charge trapping sites, such as SONOS or NROM memory cells. For example, charge retention becomes increasingly difficult as the volume of the carrier storage nodes decrease and programming and read disturbs increase. Other problems include the mere fabrication of structures for decreasing gate lengths. However, cells that rely on charge trapping sites do not exhibit interference among floating gates of neighboring cells.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for alternative memory structures and their operation.